1. Field of the Invention
The present invention relates to a data processor capable of executing saving and restoring of data held in a register at a high speed. More particularly, it relates to a data processor in which a time necessary for saving and restoring of register contents can be shortened by simultaneously saving and restoring the two register contents by one processing, when executing the instruction to transfer the data held respectively in a plurality of registers.
2. Description of the Related Art
Conventionally, in a data processor, for the purpose of accessing data used frequently at a high speed with a simple mechanism, a register file comprising about 16 general purpose registers is provided and the data being accessed frequently and the intermediate operation results are held in the register file.
In software utilizing such registers, a technique for permuting data at the conclusion of one series of processing steps and the beginning of another series of processing steps is employed. Accordingly, processing for storing the data from the registers to a memory by several numbers continuously at a time, or processings for loading the data From the memory to the registers by several numbers continuously at a time are repeated frequently.
In high-level languages such as C or Pascal, a technique of rearranging Frequently used variables into the registers at every procedure is used often. Accordingly, in software designed in these high-level languages, it is often the case that a plurality of data are stored to the memory from the registers, or conversely, a plurality of data are loaded to the registers From the memory.
Therefore, a data processor having a multi-data transfer instruction which stores a plurality of data into the memory from the registers by one instruction, or loads a plurality of data to the registers From the memory by one instruction has been proposed hitherto. In such a multi-data transfer instruction, a technique of indicating the register, to which data is to be transferred, by a register list corresponding to a bit string of "0" and "1" is used. Accordingly, it is necessary to search the register list and encode a register number to be transferred at a high speed, therefore, for this purpose an encoding circuit called a priority encoder is proposed as a hardware.
A technique of encoding the register number to be transferred from the register list at a high speed by using the priority encoder is, particularly, disclosed in, for example, U.S. Pat. No. 4,348,741.
In the conventional data processor, since the register list is searched by using the priority encoder as aforementioned, and data held in a register having a register number obtained by encoding a bit position of "1" as binary digits are transferred serially one by one, at least, the same number of transfer operations as the number of data to be transferred must be repeated.